[Libre-soc-bugs] [Bug 324] create POWER DIV pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=324

--- Comment #43 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #40)
> (In reply to Luke Kenneth Casson Leighton from comment #39)
> 
> > self.o.op is not defined, which is why i tried to find something to set it
> > to.
> > if you can run the unit test "python3 fu/div/test/test_pipe_caller.py" and
> > investigate that would be really helpful.
> 
> i went over everything that gets set up as part of self.o.core and
> it looks like all parts of DivPipeCoreInputData are established:
> <snip>
> these also get set up.  so i believe the self.o.op.eq() - presumably
> intended to be self.o.core.eq() - is redundant.

No, self.o.op.eq() was intended to copy the PowerISA opcode since that's needed
after DivPipeCore finishes its work. Notice that CoreInputData derives from
CoreBaseData, which derives from DivInputData, which should contain a field for
the PowerISA opcode, which is what I assumed self.o.op is.

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