[Libre-soc-bugs] [Bug 70] evaluate Bus Architectures

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=70

Jacob Lifshay <programmerjake at gmail.com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|FIXED                       |---
             Status|RESOLVED                    |DEFERRED

--- Comment #14 from Jacob Lifshay <programmerjake at gmail.com> ---
Why was this closed? As far as I know, we didn't decide if we were going to
implement OmniXtend (or similar cache-coherency protocols over ethernet) or not
for the 28nm SoC. Additionally, we didn't decide what cache coherent protocol
to use for inter-core communication, since wishbone is not sufficient by
itself.

Deferring till after 180nm SoC.

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