[Libre-soc-bugs] [Bug 558] gcc SV intrinsics concept

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=558

--- Comment #11 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #10)
> remenber, jacob: SIMD, RVV, SVE2 and AVX512 compiler intrinsics
> fundamentally reflect the underlying concepts of the ISA they map to.
> 
> with 188 instructions in RVV the RVV compilers will require 180x{elwidth
> permutations} minimum intrinsics to support the ISA assembly code.
> 
> the "tagging" of SV requires the *tag* concept to be recognised, and
> consequently a first alpha level prototype can get away with:
> 
> * vector tagging
> * setvl intrinsic
> * svp64 prefix context
> 
> err... that's it.
> 
> how can we get away with that? because there *are* no vector instructions:
> only prefixing.

that's all fine and good at the assembly/machine-code level, but that totally
won't work throughout the rest of the compiler, as explained by Alexandre and
me previously.

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