[Libre-soc-bugs] [Bug 558] gcc SV intrinsics concept

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=558

--- Comment #10 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
remenber, jacob: SIMD, RVV, SVE2 and AVX512 compiler intrinsics fundamentally
reflect the underlying concepts of the ISA they map to.

with 188 instructions in RVV the RVV compilers will require 180x{elwidth
permutations} minimum intrinsics to support the ISA assembly code.

the "tagging" of SV requires the *tag* concept to be recognised, and
consequently a first alpha level prototype can get away with:

* vector tagging
* setvl intrinsic
* svp64 prefix context

err... that's it.

how can we get away with that? because there *are* no vector instructions: only
prefixing.

-- 
You are receiving this mail because:
You are on the CC list for the bug.