[Libre-soc-bugs] [Bug 230] Video opcode development and discussion

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=230

--- Comment #30 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
argh, argh, ok, i have an idea.  some of VSX's instructions are 2-in 1-out
"merging" instructions, others are 1-in 2-out "splitters".

if those were added as actual instructions, which took:

* an array of vec2/3/4 as input/output
* an array of elements as output/input

and allowed this to be the *only* Function Unit that had inputs and outputs
across all 4 of those "lanes" that you can see here:

   https://libre-soc.org/openpower/sv/example_dep_matrices/

and if it was done as an FSM (not a pipeline), then it could "accumulate" its
inputs and push out outputs, without overwhelming the regfiles or the DMs, and
not take up too much space.

it would cover the type of operation from comment #27 without affecting the
scalar FU paths.

basically, operations from section 6.8.1 and 6.8.2 p254 and around there,
v3.0B, but of the form:

   mv r3.vec2, r4, VL=5
   mv r4, r2.vec4, VL=8

elwidths still settable on both src and dest.

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