[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #60 from Jean-Paul.Chaput at lip6.fr ---
(In reply to Luke Kenneth Casson Leighton from comment #59)
> https://gitlab.lip6.fr/vlsi-eda/coriolis/-/issues/25
> 
> "Katana BUG" after updating to a different setup for INT and FAST
> regfiles.  the read/write Bus is now done using a MUX followed by
> OR tree.

  The problem was due to an incorrect use of the CfgCache object,
  so the specific parameters where not taken into account.
  I put pushed the correction in commit
ee3bd54fdf0d788c8227380daa6afd8f787e7074

  Basically, the priority level was not set (default is not high
  enough to override) and anyway they were not applied.
  To apply the parameters, either explicitly call cfg.apply() or
  use the "with" construction.

  So, you did get a layout *without* the placer trying to evenly
  spread the free space, so it mostly ended up in the top right
  corner.

  As for the "looping" bug, it's a misnomer (my bad). This is not
  a bug in the normal sense. It means that the router is repeatedly
  ripping up one segment so that the algorithm has reached a dead end.
  And I have to analyse the trace to see how to avoid getting in
  that state. 

  Now it's almost ok (less then 20 failed segments).

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