[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #59 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://gitlab.lip6.fr/vlsi-eda/coriolis/-/issues/25

"Katana BUG" after updating to a different setup for INT and FAST
regfiles.  the read/write Bus is now done using a MUX followed by
OR tree.

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