[Libre-soc-bugs] [Bug 450] Create MMU from microwatt mmu.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=450

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #3)

> VHDL -> nmigen translation question, is the following correctly translated?
> or should (5 downto 4) be translated


remember that 63 downto 0 was translated as Signal(64) and that those are
accessed as 0 to 63 in that order (0 *upto* 63)?

therefore "5 downto 4" is "4 upto 5" however in python you add 1 to the end.

so "5 downto 4" becomes [4:5+1] which is [4:6]

the & operator when replacing it with Cat  is particular confusing but
basically the same 

except that constants such as x'567' are NOT inverted, those you count the
number of bits (12 in x'567') and translate it to

    Const(0x567, 12)

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