[Libre-soc-bugs] [Bug 450] Create MMU from microwatt mmu.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=450

--- Comment #3 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #2)
> (In reply to Cole Poirier from comment #1)
> > It took a very long time to manually format everything to properly to 80
> > char width, but it was worth it, it's so clear, pretty, and easy to
> > understand now.
> 
> yyep.  and now you have room on-screen to open a lot more xterms and
> see a lot more files side-by-side at the same time.
> 
> one of which is going to be common.vhdl
> 
> # entity mmu is
> #     port (
> #         clk   : in std_ulogic;
> #         rst   : in std_ulogic;
> #
> #         l_in  : in Loadstore1ToMmuType;
> #         l_out : out MmuToLoadstore1Type;
> #
> #         d_out : out MmuToDcacheType;
> #         d_in  : in DcacheToMmuType;
> #
> #         i_out : out MmuToIcacheType
> #         );
> # end mmu;
>     def __init__(self, l_in, l_out, d_out, d_in, i_out):
>         self.l_in = l_in
>         self.l_out = l_out
>         self.d_out = d_out
>         self.d_in = d_in
>         self.i_out = i_out
> 
> this needs to be:
> 
>     def __init__(self):
>         self.l_in = LoadStore1ToMMUType()
>         self.l_out = ...
>         self.d_out = ...
>         self.d_in = ...
>         self.i_out = ...
> 
> where you look in common.vhdl for Loststore1ToMmuType and turn that
> into a class that inherits from RecordObject.
> 
> have a look in.... somewhere else i've done these translations...
> soc/debug/dmi.py
> 
> and compare that to core_debug.vhdl.

Thanks, that's very helpful!

VHDL -> nmigen translation question, is the following correctly translated? or
should (5 downto 4) be translated as [5:3:-1] ? or [3:6] ?
 #       case r.shift(5 downto 4) is
         with m.Switch(r.shift[0:2]):
 #           when "00" =>
 #               sh1 := r.addr(42 downto 12);
             with m.Case(0):
                 comb += sh1.eq(r.addr[20:52])
 #           when "01" =>
 #               sh1 := r.addr(58 downto 28);

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