[Libre-soc-bugs] [Bug 448] MUL pipeline unit tests

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=448

--- Comment #55 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #54)
> (In reply to Cole Poirier from comment #53)

> this is programming.  one line at a time.  

Indeed.

> > >  initial_regs = [0] * 32
> > 
> > So this sets r0 through r31 to 0?
> 
> it initialises an array which, when handed to ISACaller, does that, yes 

Ah ISACaller, will be getting to know this module well.

> > Registers are 64 bits?
> 
> yyup.

I was 99% sure, but had a niggling doubt.

> > > what is register 0 set to by the previous line?
> > 
> > It is set to 0 because that's what all registers are initialized to.

Sorry, all registers are initialized to by the line "initial_regs = [0] * 32",
well eventually as I now understand this is an array that specifies the initial
values for ISACaller to set.

> and you asked for register 0, which was set to zero, to be RA.

Right, because:

mulli RT,RA,SI

and I asked for "mulli 1 0 X"

therefore:

RT = r1
RA = r0
X  = immediate (random.choice from test_values)

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