[Libre-soc-bugs] [Bug 448] MUL pipeline unit tests

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=448

--- Comment #54 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #53)
> 
> Going to go through point by point to confirm my understanding, below.

this is programming.  one line at a time.  
> > 
> >  initial_regs = [0] * 32
> 
> So this sets r0 through r31 to 0?

it initialises an array which, when handed to ISACaller, does that, yes 

> Registers are 64 bits?

yyup.


> > what is register 0 set to by the previous line?
> 
> It is set to 0 because that's what all registers are initialized to.

and you asked for register 0, which was set to zero, to be RA.

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