[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #52 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #51)
> (In reply to Luke Kenneth Casson Leighton from comment #50)
> > Created attachment 94 [details]
> > staggered pipeline quick drawing
> 
>   I've just commited a basic demonstrator for the recursive block
>   management. It is far from perfect and surely will exhibit bugs...
>   But I think you can start playing with it. The example is a very
>   bad placement (all the FUs in line).

that's what i thought would work.

>   I did write a very quick GUIDELINES.rst to explain some of the
>   most important points in floorplaning.

appreciated.

thank you. will try tomorrow.

>   You can extract basic gates statistics with the "stats" plugin.
>   ( Misc ==> Alpha ==> Statistics ) It will help you see which
>   blocks are big and where do the gates comes from.

ok.

>   I will now focus on the flat approach and to add the missing
>   features that we absolutely need for the TSMC run.
> 
>   It may be best to rebuild from scratch Coriolis as I moved
>   around a little the Python cumulus modules.

yes i saw this:

d6b90a70
by Jean-Paul Chaput at 2020-08-02T18:15:15+02:00
Enable Etesian to compute AB of fixed width.

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