[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #51 from Jean-Paul.Chaput at lip6.fr ---
(In reply to Luke Kenneth Casson Leighton from comment #50)
> Created attachment 94 [details]
> staggered pipeline quick drawing

  I've just commited a basic demonstrator for the recursive block
  management. It is far from perfect and surely will exhibit bugs...
  But I think you can start playing with it. The example is a very
  bad placement (all the FUs in line).

  I did write a very quick GUIDELINES.rst to explain some of the
  most important points in floorplaning.

  You can extract basic gates statistics with the "stats" plugin.
  ( Misc ==> Alpha ==> Statistics ) It will help you see which
  blocks are big and where do the gates comes from.

  I will now focus on the flat approach and to add the missing
  features that we absolutely need for the TSMC run.

  It may be best to rebuild from scratch Coriolis as I moved
  around a little the Python cumulus modules.

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