[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon Jan 4 06:44:28 GMT 2021


--- Comment #49 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Alexandre Oliva from comment #47)

> generally don't want to change their significance, only their order.  You
> seem to have got them mixed up, which may be caused by this dyslexia you
> mention, or even be the root cause thereof.

that's why i pointed you at the microwatt source code, instead.

the XNOR of MSR.LE and the ld op where byterev=0 in the CSV file (or microwatt
equivslent) gives a 1

which means: perform the bytereverse.

therefore MSByte of memory goes into LSByte of regfile.

check rhe BR column


search for the ld operation.  you will seethat the BR column for ld is zero but
ldbrx it is 1.

0 XNOR 0 is 1.  therefore bytereversing is performed.

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