[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon Jan 4 06:37:27 GMT 2021


--- Comment #48 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Alexandre Oliva from comment #43)
> luke, *please* stick to what I'm writing and suggesting, not to your
> imaginations and fears,

as long as it is not clear to me that you understand how the HDL handles BE/LE
right now (stating erroneously that it places MSByte of memory into MSByte of
regfile) we cannot proceed to the vector case.

let us stick to the scalar case for now.

can you clarify: were you stating that that is how you would *like* the scalar
execution to behave, or were you stating how you *believe* the HDL of both
microwatt and libresoc work?

You are receiving this mail because:
You are on the CC list for the bug.

More information about the Libre-SOC-ISA mailing list