[Libre-soc-isa] [Bug 213] SimpleV Standard writeup needed

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon Oct 19 23:52:27 BST 2020


--- Comment #74 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Jacob Lifshay from comment #73)
> (In reply to Luke Kenneth Casson Leighton from comment #71)
> > 
> > we _could_ conceivably do bit-level DM subdivision onto 64 bit integer regs
> > but... no, please, no :)  it makes a mess of the "Register Cache" idea,
> > unfortunately.
> it would totally work, those

oops forgot to finish:

all we need to do is treat those two mask-optimized int regs as separate from
the rest -- kinda like CTR is treated differently than the int regs.

> > 
> > whereas CRs we have the freedom *to* decide how many we want to extend it to.

the set of integer registers optimized for masking can be extended too, without
needing all the mess of CRs.

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