[Libre-soc-isa] [Bug 213] SimpleV Standard writeup needed

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon Oct 19 23:47:32 BST 2020


--- Comment #73 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #71)
> (In reply to Jacob Lifshay from comment #68)
> > > the question is, really: realistically what the heck are we doing VL at 64 for,
> > > that would use up that many CRs?
> > 
> > strncat?
> oh yeah :)  although a case could be made - my point is, i think, that
> learning from POWER10's *eight*-way multi-issue and applying it on on
> "elwidth=8 VL=16", would achieve the same end result but without overtaxing
> the regfiles.

true, though performance could be improved by keeping pipelines full with
larger VLs.
> > if we decide to used vectorized CRs we would also need instructions for
> > creating dense bitvectors from CRs for all the bitmanip goodness. Similar
> > instructions would be needed for 8-bit per lane masks. using 1-bit per lane
> > masks bypasses all that since it's already the correct type of bitvector.
> i think i kinda worked out (and showed) that this is only true - only
> practical - if the 1 bit gets its own DM row. 

exactly what I'm advocating for, except I found a way to overcome the weakness
of needing too many DM rows -- splitting the register as described in comment
53, where, for VL < 8 (or 16), it's exactly equivalent to splitting on every
bit since the DM rows are assigned ISA-level bits in a rotating interleaved

> and if you're going to do
> that, CRs already fit that bill.

so we take this hexagonal peg (CRs) and put it in the round hole (masking) --
it's technically not putting a square peg in a round hole -- it might fit
better, but it's not optimal.

> we _could_ conceivably do bit-level DM subdivision onto 64 bit integer regs
> but... no, please, no :)  it makes a mess of the "Register Cache" idea,
> unfortunately.

it would totally work, those 
> whereas CRs we have the freedom *to* decide how many we want to extend it to.

You are receiving this mail because:
You are on the CC list for the bug.

More information about the Libre-SOC-ISA mailing list