[Libre-soc-dev] parallel reduction
luke.leighton at gmail.com
Tue Sep 6 16:43:54 BST 2022
first unit test in ISACaller with Parallel Reduction REMAP produces
correct results. it was relatively straightforward to add because of
hooking the new yielder into existing REMAP infrastructure, in
it turns out that there are unexpected side-benefits: Saturate and
other modes may be applied, which on Reduction for audio and
video may prove quite important. it would not have been practical
to add all types of modes.
also inversion of the schedule order is now possible, although this
will require a new instruction encoding.
particularly tricky will be predication, which needs to be per-reg
*not* per-operation but *after* REMAP not before.
currently src/dst-step is used as an index to say whether to skip
or zero an element: that unfortunately has to change to
*post*-remapping of src/dst-step which is tricky.
it is getting there.
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