[Libre-soc-dev] [OpenPOWER-HDL-Cores] microwatt-libre-soc interoperable verilator snapshots / debugging
luke.leighton at gmail.com
Mon Jan 10 19:39:46 GMT 2022
i just thought of another good reason why this is useful, but it depends on the saved-state being in a text-editable format (not unreasonable, easily achieved)
for the simulations that Lauri helped with of ffmpeg MP3 inner functions, he asked me to get the python-based Power ISA simulator into shape such that it could actually run an actual function (in standard EABI form) this turned to be very straihhtforward:
* allow loading of LR
* allow loading of executable
* allow loading of data
* allow loading of GPRs
the LR was arranged to be out of execution range such that the return blr instruction jumped to an illegal point and you knew to terminate the simulation.
if the same file format is supported as input to verilator then it becomes possible to not only run individual functions but to also pre-prepare microwatt to be able to execute tiny unit test code-fragments from the commandline (like we do in libresoc)
extraction of the results of that execution can then be examined and confirm that they are expected (or not)
if unit tests are done as a "full binary" then the size of the preparation of the test just to run one instruction not only dwarfs the test but also could interfere.
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