[Libre-soc-dev] [OpenPOWER-HDL-Cores] microwatt-libre-soc interoperable verilator snapshots / debugging

lkcl luke.leighton at gmail.com
Sun Jan 9 19:38:57 GMT 2022

On January 9, 2022 3:28:41 PM UTC, Jacob Lifshay <programmerjake at gmail.com> wrote:

>was filled). If the TLB is too messed up, you can add a TLB consistency
>check to the simulation and break when it becomes inconsistent.

the current bug under investigation is at instruction 10,000,000 and is one of the very first instructions executed by linux when MSR.DR and MSR.IR are set.

the first few instructions are fine.  the MMU walk  which loaded the instructions (creating an ITLB entry) are also fine.

i can see the MMU RADIX walk loading exactly the right values from memory because the diff of MW vs LS shows them to be the same.

what i do not know is why the exact same "std" instruction is loaded and run again and again, without end.

what i do not need is for an instruction MMU walk to end up reloading and potentially interfering with the attempt to replicate the *Data* MMU walk on startup-and-restore

having the PTE entries already pre-loaded by the startup process would stop that interference.


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