[Libre-soc-dev] effect of more decode pipe stages on hardware requirements for execution resources for OoO processors

lkcl luke.leighton at gmail.com
Wed Feb 16 20:02:40 GMT 2022

On February 16, 2022 7:13:18 PM UTC, Jacob Lifshay <programmerjake at gmail.com> wrote:
>On Wed, Feb 16, 2022, 11:01 lkcl <luke.leighton at gmail.com> wrote:
>> i note - and am quite concerned - that you did not acknowledge what i
>> said.
>i did read it, if i disagreed i'd usually have said something. in
>we now mostly agree, we just had different underlying assumptions.

too many variables, means it is almost impossible to ascertain where the discrepancies might lie. once a baseline is estsblishes, variances can be introduced but it is crucial to establish - and confirm - a first sync.

>yup...the FIFO is mostly a quirk of power-cpu-sim's design, I'd
>just stall the fetch/decode pipe instead of having a FIFO in a real
>unless the FIFO had some benefit such as repeating a loop automatically
>from the FIFO rather than having to read it from the icache again each

it would be better i feel to have direct access to full cache line(s) and to be able to read from them.

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