[Libre-soc-dev] effect of more decode pipe stages on hardware requirements for execution resources for OoO processors

Jacob Lifshay programmerjake at gmail.com
Wed Feb 16 19:13:18 GMT 2022

On Wed, Feb 16, 2022, 11:01 lkcl <luke.leighton at gmail.com> wrote:

> i note - and am quite concerned - that you did not acknowledge what i
> said.

i did read it, if i disagreed i'd usually have said something. in summary,
we now mostly agree, we just had different underlying assumptions.

now, that aside, the big downside of dropping instructions into a FIFO
> (rather than into RSes) is that you absolutely cannot put anything
> from that FIFO out of order: you absolutely *must* drop instructions
> in-order from the FIFO into the Dependency Matrices.  and, once the
> FIFO is full, you absolutely have to stall, there's nothing you can
> do.

yup...the FIFO is mostly a quirk of power-cpu-sim's design, I'd probably
just stall the fetch/decode pipe instead of having a FIFO in a real cpu,
unless the FIFO had some benefit such as repeating a loop automatically
from the FIFO rather than having to read it from the icache again each


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