[Libre-soc-dev] effect of more decode pipe stages on hardware requirements for execution resources for OoO processors

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed Feb 16 00:49:03 GMT 2022

On Wed, Feb 16, 2022 at 12:41 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:

> an illustration of the problem can be done by making two hypothetical
> 8-way-multi-issue processors:
> 1) the decode stage take 8 stages and the execution only 1.
> 2) the decode stage is 1 clock and execution only 1.

assume that registers are decoded at stage 1 in both cases,
such that all 8 instructions may be successfully issued to
in-flight buffers per clock cycle.

also assume that both the LD and ST are satisfied from cache
in 1 clock cycle.


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