[Libre-soc-dev] effect of more decode pipe stages on hardware requirements for execution resources for OoO processors
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Wed Feb 16 00:41:15 GMT 2022
On Wed, Feb 16, 2022 at 12:15 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
> luke & I were arguing about wether additional decode pipe stages
> necessitate more reorder buffers, rename registers, and other execution
> hardware buffers. I made this wiki entry with pipe timing diagrams to
> support my position that, ignoring branch misprediction, no additional
> execution resources are needed.
now make it 8-way multi-issue, such that at any one point it is easy
to advance-saturate for example 5 copies of a 4-instruction loop
(LD, op, ST, branch)
an illustration of the problem can be done by making two hypothetical
1) the decode stage take 8 stages and the execution only 1.
2) the decode stage is 1 clock and execution only 1.
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