[Libre-soc-dev] Coriolis 2 - Tutorials and check

Santhosh Kumar V V . 123040015 at sastra.ac.in
Wed Aug 24 13:56:35 BST 2022

Thankyou very much for your kind support throughout the process sir, I will
progress as you instructed and update you.

On Wed, Aug 24, 2022 at 5:18 PM lkcl <luke.leighton at gmail.com> wrote:

> On Wed, Aug 24, 2022 at 6:00 AM Santhosh Kumar V V .
> <123040015 at sastra.ac.in> wrote:
> >
> > Good Afternoon sir, I found the GDS-II file and it works successfully, I
> can see the chip_r GDS-II layout.
> hooraaay.  bear in mind, that is with "ghost" cells, and a fake layer
> stack. you can't actually send it to a Foundry, they will not have that
> stack, and the cells will be blank.
> if you want to replicate the 180nm GDS-II files you need an NDA
> in place with TSMC, first.
> > As I was out of station for the last few days, I couldn't reply to your
> mail, thankyou sir.
> >
> > Sir, Now the environment is set up, Shall I try a custom design and make
> it as a chip ?
> sure, why not! :)
> there are a number of diferent directions you can go, here.  perhaps
> the simplest is to build the adder example,
> https://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/tree/master/benchs/adder
> or any of the others in the alliance_check_toolkit, and to confirm that
> the HDL
> (verilog usually) is what you expect.
> bear in mind you actually have to define the chip corona yourself
> (in python - see doDesign.py) and so on, so it is best to start from
> an existing (small!) design initially, to get a feel for how things work.
> also please bear in mind that in the past year there has been migration
> to python3.  if you use *anything* from coriolis2 in the past year you are
> on your own, as i was working over 15 months ago on this, using python2.
> l.

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