[Libre-soc-dev] daily kan-ban update 08aug2022
Tobias Platen
libre-soc at platen-software.de
Mon Aug 8 20:19:24 BST 2022
today: trying to get a result when running "vvp -n simsoc -fst-speed",
hangs for a long time, guess I am doing something wrong here.
./top.v:206639: warning: Instantiating module EHXPLLL with dangling
input port 2 (CLKFB) floating.
./top.v:206639: warning: Instantiating module EHXPLLL with dangling
input port 3 (PHASESEL1) floating.
./top.v:206639: warning: Instantiating module EHXPLLL with dangling
input port 4 (PHASESEL0) floating.
./top.v:206639: warning: Instantiating module EHXPLLL with dangling
input port 5 (PHASEDIR) floating.
./top.v:206639: warning: Instantiating module EHXPLLL with dangling
input port 6 (PHASESTEP) floating.
./top.v:206639: warning: Instantiating module EHXPLLL with dangling
input port 7 (PHASELOADREG) floating.
./top.v:206639: warning: Instantiating module EHXPLLL with dangling
input port 8 (STDBY) floating.
./top.v:206639: warning: Instantiating module EHXPLLL with dangling
input port 9 (PLLWAKESYNC) floating.
./top.v:206639: warning: Instantiating module EHXPLLL with dangling
input port 11 (ENCLKOP) floating.
./top.v:206639: warning: Instantiating module EHXPLLL with dangling
input port 12 (ENCLKOS) floating.
./top.v:206639: warning: Instantiating module EHXPLLL with dangling
input port 13 (ENCLKOS2) floating.
./top.v:206639: warning: Instantiating module EHXPLLL with dangling
input port 14 (ENCLKOS3) floating.
./top.v:230306: warning: Port 3 (data_in) of uart_rfifo expects 8 bits,
got 11.
./top.v:230306: : Pruning 3 high bits of the expression.
./top.v:230306: warning: Port 4 (data_out) of uart_rfifo expects 8
bits, got 11.
./top.v:230306: : Padding 3 high bits of the expression.
./top.v:229705: warning: Port 4 (wb_dat_i) of uart_top expects 32 bits,
got 8.
./top.v:229705: : Padding 24 high bits of the port.
./top.v:229705: warning: Port 5 (wb_dat_o) of uart_top expects 32 bits,
got 8.
./top.v:229705: : Padding 24 high bits of the port.
./top.v:229705: warning: Port 10 (wb_sel_i) of uart_top expects 4 bits,
got 1.
./top.v:229705: : Padding 3 high bits of the port.
src/simsoctb.v:92: warning: Port 11 (ddr3_0__a__io) of top expects 13
bits, got 14.
src/simsoctb.v:92: : Padding 1 high bits of the expression.
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