[Libre-soc-dev] Greetings

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri Nov 19 07:40:23 GMT 2021

crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Fri, Nov 19, 2021 at 7:16 AM D. Mitch Bailey
<d.bailey at shuharisystem.com> wrote:
> Greetings,
> Joining the mailing list after watching Jean-Paul Chaput's and Luke
> Leighton's presentations at Matt Venn's Opentapeout conference.

nice to hear from you, Mitch

> I'm a backend layout verification/EDA developer familiar with Cadence
> and Calibre. I've also written an open-source program that has some of
> the capabilities of Calibre-PERC (I call it CVC - Circuit Validity
> Checker, but unfortunately there seems to be a verilog simulator that's
> also called CVC.).

oh whoops :)

> It detects static shorts, possible forward biased
> diodes and mosfet bulk connections, Hi-Z inputs (including outputs from
> cutoff regions), incorrect gate voltages for multipower designs, EOS
> (electrical overstress) errors, and a few others.


> For the past year, I've been working intermittently on a device level
> LVS flow using magic/netgen for google/efabless/skywater and integrating
> CVC into that design flow.


> If Libre-SOC has a chip-level spice netlist publicly available, I'd be
> willing to check it for errors.

it's auto-generated as part of the results created from coriolis2,
the auto-generated output is (compressed) a massive 20mb archive

now, that's the "Libre" (parallel) version, done using nsxlib: it's not
the one using the (NDA'd) TSMC 180nm Cell Library.  there is another
version that can be auto-generated: from C4M-FreePDK45.

i'd be very interested to hear what results you get.



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