[Libre-soc-dev] Greetings

D. Mitch Bailey d.bailey at shuharisystem.com
Fri Nov 19 06:17:57 GMT 2021


Joining the mailing list after watching Jean-Paul Chaput's and Luke 
Leighton's presentations at Matt Venn's Opentapeout conference.

I'm a backend layout verification/EDA developer familiar with Cadence 
and Calibre. I've also written an open-source program that has some of 
the capabilities of Calibre-PERC (I call it CVC - Circuit Validity 
Checker, but unfortunately there seems to be a verilog simulator that's 
also called CVC.). It detects static shorts, possible forward biased 
diodes and mosfet bulk connections, Hi-Z inputs (including outputs from 
cutoff regions), incorrect gate voltages for multipower designs, EOS 
(electrical overstress) errors, and a few others.

For the past year, I've been working intermittently on a device level 
LVS flow using magic/netgen for google/efabless/skywater and integrating 
CVC into that design flow.

If Libre-SOC has a chip-level spice netlist publicly available, I'd be 
willing to check it for errors.

D. Mitch Bailey

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