[Libre-soc-dev] Gigabit Router Pinmux Considerations

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Nov 4 14:32:45 GMT 2021

crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Thu, Nov 4, 2021 at 2:07 PM Andrey Miroshnikov
<andrey at technepisteme.xyz> wrote:
> Hi All,
> Yesterday after the chat I did a quick draft of the pinmux page for the
> router:
> https://libre-soc.org/crypto_router_pinmux/
> I only included an estimate for the required number of pins (before any
> muxing). While writing this email actually answered a lot of my
> questions and updated the pin counts hahaha
> The page is also linked to main crypto router page:
> https://libre-soc.org/crypto_router_asic/

brilliant.  i've just added 3.3v IO power/gnd (10 each), because of the size of
the ASIC i've upped the 1.8v core power to 13.  it's going to be BIG.
at least...
70 mm^2 which will be around 8x9mm

i've also added some cross-refs to the shakti peripheral pages

> Currently checking the pins required for various interfaces (which I'll
> add to the wiki page once I create class for the router ASIC).

if we can possible avoid doing a pinmux (the multiplexer) it would save
about... 6-8 weeks.  so is worth _not_ doing.

> Here are some questions that I have:
> - Why was does the RGMII interface we use require 20 pins? - Last night
> I found a 12 pin version where some of the extra signals are encoded
> using the data lines (perhaps our PHY doesn't support this, see Section
> 3.4:
> https://web.pa.msu.edu/hep/atlas/l1calo/hub/hardware/components/micrel/rgmii_specification_hp_v1.3_dec_2000.pdf)

that diagram is too simplified.  you missed out MDIO (12+2) and the
diagram misses out TXERR and RXERR

this is a better example:


it's not _exactly_ 20, i misremembered, but it's not 12 either.

> - Is the SDRAM1 interface the same as the one used in LS180?.

yes.  we'll need this or an adapted version of it.

if necessary the litex migen one can be adapted / converted to nmigen.

> - Which package is going to be used for the router ASIC? - During the
> meeting I heard QFP, but the pincount was not specified.

let me find it. i'll upload to ftp.libre-soc.org and put it on the wiki,
it was from Staf about 10 months ago.

basically there are standard packages and for practical reasons we
have to fit one of those.

max 256 pins.

> - Are all the interfaces mentioned in the crypto router page required? -
> I have not included PWM in my calculations. PWM might be handy for LEDs
> (that's where I've usually seen them used for).

yes.  cut GPIO to 8.  i didn't add PWM last time due to time constraints,
there are some things "essential" others "nice to have".

> Should I also put this under a new bug somewhere?

yes, good call, sub-bug of 589, cross-ref 690 because it's relevant.


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