[Libre-soc-dev] ISA analysis
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sun May 9 11:43:57 BST 2021
On Sun, May 9, 2021 at 6:18 AM Lauri Kasanen <cand at gmx.com> wrote:
> On Sun, 9 May 2021 00:10:34 +0100
> Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> > https://news.ycombinator.com/item?id=24459314
> > fascinating. particularly that the alibaba team had to add custom
> > addressing modes to RISCV in order to achieve decent performance.
> For reference:
> First, we support register + register addressing mode, and
> support indexed load and store instructions.
yep, OpenPOWER has that.
> This type of
> instruction extension reduces the usage of the registers for
> calculation and reduces the number of instructions for address
and OpenPOWER has LD/ST-with-update which saves even further
> thereby effectively accelerating the data access
> of a loop body. Second, unsigned extension during address
> generation is supported.
> Otherwise, the basic instruction set
> does not support direct unsigned extension from 32-bit data
> to 64-bit data, resulting in too many shift instructions.
let's take a look at v3.1
p56 plwa (and others), they allow EA to be computed from a 34-bit
immediate, and also allow relative to the PC.
so, not the same thing.
> So not x86's "add this and multiply that"
> address-struct-member-in-an-array-of-structs addressing after all.
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