[Libre-soc-dev] ISA analysis
cand at gmx.com
Sun May 9 06:20:07 BST 2021
On Sun, 9 May 2021 00:10:34 +0100
Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> fascinating. particularly that the alibaba team had to add custom
> addressing modes to RISCV in order to achieve decent performance.
First, we support register + register addressing mode, and
support indexed load and store instructions. This type of
instruction extension reduces the usage of the registers for
calculation and reduces the number of instructions for address
generation, thereby effectively accelerating the data access
of a loop body. Second, unsigned extension during address
generation is supported. Otherwise, the basic instruction set
does not support direct unsigned extension from 32-bit data
to 64-bit data, resulting in too many shift instructions.
So not x86's "add this and multiply that"
address-struct-member-in-an-array-of-structs addressing after all.
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