[Libre-soc-dev] RFC: Make sm=m by default on twin predication for SVP64 assembly
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Mon Mar 22 16:37:26 GMT 2021
On Monday, March 22, 2021, Cesar Strauss <cestrauss at gmail.com> wrote:
> In SVP64 assembly, on twin predication, srcmask (sm) seems to be set to
> "always" by default, if not specified.
the four combinations are:
* no masks (both always)
* sm set, dm=always
* sm=always, dm set
* both set.
basically if one of the masks is not specified, they must each
independently be set to "always".
> This is in contrast to single
> predication, where srcmask is implicitly set to destmask (m).
> So, this will trigger a VEXPAND:
> sv.extsb/m=r3 5.v, 9.v
yes it's odd, the *source* triggers VEXPAND, the *dest* triggers VREDUCE.
> ... which is not obvious by just looking at it.
> I propose to have to explicitly state that sm=~0 or sm=all1, when we do
> want a VEXPAND:
> sv.extsb/m=r3/sm=all1 5.v, 9.v
this is muuch longer, which will result in more processing power used, some
of the options alreafy take up an alarming line length
i don't have a problem with adding both those syntaxes for clarity /
> ... and make the first example identical to:
> sv.extsb/m=r3/sm=r3 5.v, 9.v
> ... which corresponds to single predication.
> In other words, twin predication only happens when "sm" is explicitly
> present in the instruction (and different from "m").
twin predication is a property of the instruction.
> Otherwise, it is
> simple predication, even if the instruction is twin-predication capable.
ok so one solution is to introduce this:
m=XX # 2pred sets both
sm and dm are only possible to set on 2pred.
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