[Libre-soc-dev] RFC: Make sm=m by default on twin predication for SVP64 assembly
cestrauss at gmail.com
Mon Mar 22 13:23:03 GMT 2021
In SVP64 assembly, on twin predication, srcmask (sm) seems to be set to
"always" by default, if not specified. This is in contrast to single
predication, where srcmask is implicitly set to destmask (m).
So, this will trigger a VEXPAND:
sv.extsb/m=r3 5.v, 9.v
... which is not obvious by just looking at it.
I propose to have to explicitly state that sm=~0 or sm=all1, when we do
want a VEXPAND:
sv.extsb/m=r3/sm=all1 5.v, 9.v
... and make the first example identical to:
sv.extsb/m=r3/sm=r3 5.v, 9.v
... which corresponds to single predication.
In other words, twin predication only happens when "sm" is explicitly
present in the instruction (and different from "m"). Otherwise, it is
simple predication, even if the instruction is twin-predication capable.
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