[Libre-soc-dev] Libre-SOC SVP64 first Cray-style Vector loop successful
cestrauss at gmail.com
Sun Mar 7 17:39:42 GMT 2021
Em 07/03/2021 10:24, Luke Kenneth Casson Leighton escreveu:
> with many thanks and congratulations to Cesar for getting the first basic
> Cray-style Vector Loop operational in HDL, on top of OpenPOWER v3.0B and
> passing its first unit tests.
I'm glad for giving my small contribution, but it was really a team
effort, congratulation to us all.
Especially after Luke lead all the preparatory work on the Python
Assembler, Simulator, HDL Decoder, Test Cases, etc., so I started with
most supporting pieces already in place. I really only helped placing
the last remaining piece of this current milestone (improve an existing
HDL State Machine to run a For-Loop on the Fetch and Execute stages).
Also, of course, thanks to everyone else on the team for helping the
project get this far, with the OpenPOWER Simple-V specification in
place, the Computation Units, Pipelines, the Decoder, Simulator, IEEE
754 Floating Point, the project infrastructure, documentation, as well
as well as the ongoing work on GCC and Binutils, Vulkan drivers, Caches,
MMU, FPGA testing, unit testing, formal verification, nMigen
improvements, general support, helpful insights and pointers,
Looking forward for the way still to follow.
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