[Libre-soc-dev] [RFC] horizontal SVP64 vectors

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Jul 8 14:17:03 BST 2021

On 7/8/21, Richard Wilbur <richard.wilbur at gmail.com> wrote:

> Is this version of “REMAP” what you are proposing to use to implement ZOLC?

REMAP stays as it is, it gets "joined" by Vertical-first mode, the
combination effectively being very similar to the "lowest levels" of
ZOLC concepts (read the 2007 paper, it explains there are 3 types)

> Sounds like a cool idea.  Very easily applicable to quite a number of
> algorithms without the introduction of a lot of new instructions.

yes, exactly, without the massive deviation from standard compilers.

interestingly ST Micro did actually put ZOLC into commercial silicon.

> This reminds me of a concept I proposed to some classmates back in
> undergraduate days:  a massively serial processor (as opposed to massively
> parallel processors).

sounds exactly like the Aspex ASP i worked with in 2003.

programming for that was measured in **DAYS** per line of assembler.
productivity of 10 days per line of assembler was good going.  yes,

>  The basic idea is to have a number of processing
> elements which you configure as you decode a sequence of instructions and
> connect up register access/dependencies.

hmmm there was another processor around that did this. it didn't have
"actual registers" but everything instead was expressed as chains: use
the result of this computation as the input to *this* one etc. where
the chains started from LOAD and ended at STORE.


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