[Libre-soc-dev] [RFC] horizontal SVP64 vectors
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Thu Jul 8 13:30:26 BST 2021
On 7/8/21, whygee at f-cpu.org <whygee at f-cpu.org> wrote:
> to registers through the register-mapped memory : the vectors can be ANY
> and reside in cache, instead of requiring crazy numbers of registers...
that makes for a memory bottleneck on the top speed achievable,
because the fanout to addressing is larger than it would be for
registers or a register cache.
if you can solve that then modern high performance could be achieved.
the STAR-100 was a memory only vector engine and it was punished by
the extra memory lookups.
Cray's work was at a time whem memory was the same speed as the processor.
now it is a 10x to 150x difference.
More information about the Libre-soc-dev