[Libre-soc-dev] [RFC] horizontal SVP64 vectors

Jacob Lifshay programmerjake at gmail.com
Wed Jul 7 21:49:44 BST 2021

On Wed, Jul 7, 2021, 10:12 Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> Horizontal Vectorisation is a lot more generic and has far more
> applications.

Incrementing PC will be orders of magnitude more complex, since you might
have to modify the rest of the fetch pipeline to handle it, and you have to
correctly handle incrementing over 32/64-bit instructions, and dealing with
the branch predictor, etc., etc., etc.

I'd suggest limiting it to 2 (or maybe 4 if we're extra crazy) contiguous
instructions which can be decoded and stored in a temporary buffer,
trapping before executing any if they all can't be fetched/decoded, then
replayed out of that buffer instead of re-fetching them. The buffer can
just be re-loaded if interrupted by something. All branches, isync, and
other special instructions can just be made to trap.

After the hardware loop finishes, execution must resume after the last
instruction in the loop, don't finish the loop then start executing
somewhere in the middle of the loop.

This honestly sounds like excessive feature creep, but fast FFTs! oh,


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