[Libre-soc-dev] Simple-V svp64 draft spec

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat Jan 30 13:09:06 GMT 2021

On Sat, Jan 30, 2021 at 1:41 AM Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> this was done consistently right across the board, because it turns out
that all placement of RS into in3_sel leaves in1_sel empty in all entries
in decode1.vhdl

"done consistently" was a clue.  i just checked:

        --          unit     internal      in1         in2          in3
        38 =>       (LDST,   OP_STORE,     RA_OR_ZERO, CONST_SI,    RS,

this is not altered (microwatt-libresoc consistent for RS) and neither were
any other LD/STs.

        --          unit     internal      in1         in2          in3
        26 =>       (ALU,    OP_XOR,       NONE,       CONST_UI,    RS,

this *was* altered - and anything else that had RS in in3, where in1 was
NONE, were *consistently* moved from in3 to in1.  Logical, Shift,
sign-extend, the lot.

consequently, a simple algorithm when loading the CSV files can be deployed:
    if in1==RS and in3==NONE:
        in1=NONE, in3=RS

and we're good :)


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