[Libre-soc-dev] Simple-V svp64 draft spec

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat Jan 30 01:41:42 GMT 2021

On Friday, January 29, 2021, Luke Kenneth Casson Leighton <lkcl at lkcl.net>

>  when 30 =>
>      v.decode := decode_op_30_array(to_integer(unsigned(f_in.insn(4
downto 1))));
>      v.svp64decode :=
decode_op_svp64_30_array(to_integer(unsigned(f_in.insn(4 downto 1))));
> allo Paul,

nuts! Paul i must apologise, if you recall in LibreSOC there are 12
separate pipelines, Shift for example is completely separate from Add.

with Shift only technically having 2 input registers one of which was RS we
*moved* RS into position *one* (in1_sel) of the CSV files (equivalent to

[why have 3 register pipeline inputs, one of which is always zero/unused]

this was done consistently right across the board, because it turns out
that all placement of RS into in3_sel leaves in1_sel empty in all entries
in decode1.vhdl

consequently if i autogenerate the decode_sv_rom_type_t information from
the LibreSOC CSV files without taking these differences into consideration
the results will be meaningless.

this will take me a bit more time, apologies.


crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

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