[Libre-soc-dev] daily kan-ban update 27dec2021

Luke Kenneth Casson Leighton lkcl at lkcl.net
Tue Dec 28 03:01:46 GMT 2021

On Mon, Dec 27, 2021 at 7:30 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:

> next is an invalid table entry (garbage read), checking that the
> right interrupt is created (0x300) and DAR and DSISR are
> set, which at the moment they are not.

microwatt mmu.bin tests 5 and 6 involve a mis-aligned LD/ST which
crosses over from one (valid) page table entry to another that has
*not* been created.

we do not have misaligned memory support in Loadstore1: this was
what the PortInterface Splitter was for: to create *pairs* of *independent*
LDST requests, but it has not been added in.

i am skipping tests 5 and 6 for now, and everything up to 12 passes,
which is where instruction-side (MSR.IR) starts.

investigating that next.


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