[Libre-soc-dev] hunting around to connect up the dcache / mmu

lkcl luke.leighton at gmail.com
Tue Apr 27 14:48:39 BST 2021

today i am going through code i wrote over a year ago to see how to
connect up the PortInteface for LD/ST into the MMU.  presently, dcache
is receiving the request, but because it is not hooked up to the
Wishbone Bus, we're not getting a response.

right now i have no idea how the damn thing's getting its requests from! :)

basically the same process i went through with Minerva, adapting
Libre-SOC to Minerva's Load-Store interface, the exact same thing has
to be done with Microwatt.


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