[Libre-soc-dev] Update on Coriolis & LS180.
luke.leighton at gmail.com
Sun Apr 25 18:45:37 BST 2021
On Sun, Apr 25, 2021 at 5:56 PM Jean-Paul Chaput
<Jean-Paul.Chaput at lip6.fr> wrote:
> On Sun, 2021-04-25 at 15:48 +0100, lkcl wrote:
> > On Sunday, April 25, 2021, Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr> wrote:
> > > At the time being, you cannot perform a "make lvx" because we don't have
> > > a GDS (real) layout extractor.
> > ahh ok.
> > >
> > > > is that how FlexLib is *supposed* to work?
> > > >
> > > > i take it, you have run completed PnR "make lvx" followed by "make view" on say
> > > > experiments10_verilog/freepdk45?
> > >
> > > No, I just made the layout.
> > i never see any routes, which kinda defeats the object of the exercise.
> Do the P&R complete? (on the text screen).
> If so, maybe it is a "zoom"
> problem. What happens if you zoom into the core, do the wires starts
> to appear?
i cannot view it. on running "make view", cgt says:
Unable to find iopadvss
the last time i "fixed" this, it involved actually creating (fake)
iopadvss.ap, etc. etc. etc., plus FlexLib dio_x0.ap etc. etc. etc. all
of which took some doing, but "worked"....
ah hang on, i still have the files. after copying them into the main
subdirectory, i can run "make view".
there are zero nets. *this is even after the routing has completed*
likewise, running the command i created, here, *there are no nets*:
you can see, in the program, that it is calling Horizontal.create and
... it's just that if you then look at the AP file *it has no nets*.
> They are not "ghosts" (abstract), the problem is their connectors in
> METAL1 won't be at the same place as the real cells so all terminals
> connexions will be wrong. And, in fact everything will be misaligned.
... but it will "work". as long as topologically, the nets complete,
it gives me an opportunity to "stay ahead" of where you are - to find
problems in advance of you running into them.
if i do not do this, it will be you that runs into them (under NDA),
and you will *not be able to tell me the full details*.
> > as long as i can complete the PnR, which will allow me to extract the netlist back out
> > and then place that through cocotb i can help validate the design.
> My understanding was that you where to provides us with validated
> patterns for cocotb with the pre-routed netlist and we (Staf or LIP6)
> will do the post-routing simulations with them.
yes - the issue you will encounter is that if you use just one machine
(even an intel i9 4.8ghz) it will take about 8 weeks to *compile the
program* (ghdl or verilator) and cause that machine to melt if it has
anything less than 128 GB of RAM.
i have registered a team with fed4fire which gives us cluster
supercomputer access across the world: this will help.
before getting to that, i'd like to make sure that it stands a chance
> Maybe we can find a way to give you the post-layout netlists.
bear in mind i will need to upload them to world-wide federated
this will be the *only way* we can get the simulations to compile in a
sane amount of time.
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