[Libre-soc-dev] Update on Coriolis & LS180.
Jean-Paul.Chaput at lip6.fr
Sun Apr 25 17:56:48 BST 2021
On Sun, 2021-04-25 at 15:48 +0100, lkcl wrote:
> On Sunday, April 25, 2021, Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr> wrote:
> > At the time being, you cannot perform a "make lvx" because we don't have
> > a GDS (real) layout extractor.
> ahh ok.
> > > is that how FlexLib is *supposed* to work?
> > >
> > > i take it, you have run completed PnR "make lvx" followed by "make view" on say
> > > experiments10_verilog/freepdk45?
> > No, I just made the layout.
> i never see any routes, which kinda defeats the object of the exercise.
Do the P&R complete? (on the text screen). If so, maybe it is a "zoom"
problem. What happens if you zoom into the core, do the wires starts
> > This is where we have to stop (in public
> > mode) for now if we use real layout (see above).
> > You may have been mislead by the fact that AP files have been genarateds,
> > but they are completely wrong. I should prevent that i real mode.
> i don't mind if they're wrong, as long as they are approximate (or "ghost")
They are not "ghosts" (abstract), the problem is their connectors in
METAL1 won't be at the same place as the real cells so all terminals
connexions will be wrong. And, in fact everything will be misaligned.
> as long as i can complete the PnR, which will allow me to extract the netlist back out
> and then place that through cocotb i can help validate the design.
My understanding was that you where to provides us with validated
patterns for cocotb with the pre-routed netlist and we (Staf or LIP6)
will do the post-routing simulations with them.
Maybe we can find a way to give you the post-layout netlists.
> if i cannot do that i cannot check for errors in that process before it has to be run
> "for real" on the 180nm.
> (it takes an insane amount of time to build the simulations post PnR)
.-. J e a n - P a u l C h a p u t / Administrateur Systeme
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