[Libre-soc-dev] cxxsim with jtag connections

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat Apr 10 21:40:10 BST 2021

there are a couple of bugs in cxxrtl that need sorting, and in the meantime
i have returned to ghdl in cocotb.

the compile times for blif2vst-generated VHDL, where blif files contain
gate-level designs, are stunning: 20 minutes.  then it takes a further 20
minutes just to start the simulation and connect up the VPI interface.
binary size of the ghdl executable is 200 mb.

post-layout is almost another order of magnitude larger than that.  just
the source code VHDL file of the litex infrastructure is 60 mb.


crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

More information about the Libre-soc-dev mailing list