[Libre-soc-dev] cxxsim with jtag connections

[Luke Kenneth Casson Leighton]

there are a couple of bugs in cxxrtl that need sorting, and in the meantime
i have returned to ghdl in cocotb.

the compile times for blif2vst-generated VHDL, where blif files contain
gate-level designs, are stunning: 20 minutes.  then it takes a further 20
minutes just to start the simulation and connect up the VPI interface.
binary size of the ghdl executable is 200 mb.

post-layout is almost another order of magnitude larger than that.  just
the source code VHDL file of the litex infrastructure is 60 mb.

l.



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