[Libre-soc-dev] Running the libre-soc CPU under cxxsim
cestrauss at gmail.com
Tue Sep 22 11:18:22 BST 2020
Em 19/09/2020 18:58, Luke Kenneth Casson Leighton escreveu:
> On Sat, Sep 19, 2020 at 10:41 PM Cesar Strauss <cestrauss at gmail.com> wrote:
>> Note that "nmigen.sim.pysim" and "nmigen.sim.cxxsim" were never present
>> in a released nMigen version, so the change in API, in the middle of a
>> development cycle, is warranted.
> ok so we need a big patch to get up-to-date, first. i am holding
> back, not updating nmigen master regularly in case it introduces bugs
> (like it did 2 months ago).
>>> really this should be an environment variable
>>> import os
>>> sim = Simulator(m, engine=os.environ.get('NMIGEN_SIM_MODE"))
>> This is exactly the way that the simulator API now works.
Per discussion above, found a way to conditionally switch to cxxsim,
without losing backwards compatibility with earlier nMigen git versions.
Applied to src/soc/experiment/alu_fsm.py, as an example.
commit 70cee4d6e7d454c5378b455dd8a2779dbd82adcd (HEAD -> master,
Author: Cesar Strauss <cestrauss at gmail.com>
Date: Mon Sep 21 08:47:13 2020 -0300
Port soc.experiment.alu_fsm to the new way of invoking cxxsim
To use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell.
Be sure to check out the cxxsim branch of nMigen, and update yosys
to the latest commit as well.
To use pysim, just keep NMIGEN_SIM_MODE unset. This should be
backwards compatible to old developer versions of nMigen.
Alternatively, when using a recent developer version,
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