[Libre-soc-dev] daily kan-ban update 14sep2020

Luke Kenneth Casson Leighton lkcl at lkcl.net
Tue Sep 15 08:51:12 BST 2020

On Tue, Sep 15, 2020 at 3:21 AM Cole Poirier <colepoirier at gmail.com> wrote:

> > i am however noticing that cache entries are being overwritten which has me
> > going "hmm" somewhat.
> Probably some small fiddly but I mistranslated...

no, i think it's down to the PLRU.  something odd going on i haven't
been able to work out.

> > still, leaving that aside the next thing is to try connecting up to
> > PortInterface and see how that goes.
> That should be exciting! Can you do a review of icache.py? There’s some
> fiddle bits that I’m getting stuck on.

exactly the same thing as yesterday.  word_select needed.

can you look at dcache.py, and whereever i've put "# XXX".

> > also i looked at litex and how to add an ASIC style platform, it may just
> > be a matter of defining the pins.
> >
> Very interesting, how would this differ from the current fpga platform?

derive from generic platform not FPGA platform class.  stops creation
of bitstream, does not try to add FPGA PLLs.

result is verilog generation with nothing but pins which is exactly
what we want.


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