[Libre-soc-dev] daily kan-ban update 14sep2020
colepoirier at gmail.com
Tue Sep 15 03:21:13 BST 2020
On Monday, September 14, 2020, Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> wrote a unit test that combines the mmu and dcache modules, and after
> spotting a couple of brackets missing on | and == it actually worked.
Whoops! Cool that it’s actually working... sort of!
> i am however noticing that cache entries are being overwritten which has me
> going "hmm" somewhat.
Probably some small fiddly but I mistranslated...
> still, leaving that aside the next thing is to try connecting up to
> PortInterface and see how that goes.
That should be exciting! Can you do a review of icache.py? There’s some
fiddle bits that I’m getting stuck on.
> also i looked at litex and how to add an ASIC style platform, it may just
> be a matter of defining the pins.
Very interesting, how would this differ from the current fpga platform?
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