[Libre-soc-dev] Silly question

[Jacob Lifshay]

On Mon, Sep 14, 2020, 10:40 Cole Poirier <colepoirier at gmail.com> wrote:

> On Mon, Sep 14, 2020 at 10:34 AM Jacob Lifshay <programmerjake at gmail.com>
> wrote:
> > a nmigen Signal is the representation used for vhdl std_logic and integer
> > iirc, so to_integet most likely translates to a no-op.
>
> Ok with you there, I guess what I really need to know is the nmigen
> way of interpreting an nmigen Slice as a python integer value so that
> it can be used as a slice index. Currently getting the following error
> with the following code (icache lines 366-371):
>

You'd want Value.bit_select or Value.word_select for the general case, for
this particular case you'd want `data.word_select(word, 32)` iirc

```
> def read_insn_word(addr, data):
>     print("addr ", addr)
>     print("data ", data)
>     word = addr[2:INSN_BITS+2]
>     print("word ", word)
>     return data[word * 32:32 + word * 32]
>


Jacob

>