[Libre-soc-dev] Silly question

Cole Poirier colepoirier at gmail.com
Mon Sep 14 18:40:03 BST 2020

On Mon, Sep 14, 2020 at 10:34 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
> a nmigen Signal is the representation used for vhdl std_logic and integer
> iirc, so to_integet most likely translates to a no-op.

Ok with you there, I guess what I really need to know is the nmigen
way of interpreting an nmigen Slice as a python integer value so that
it can be used as a slice index. Currently getting the following error
with the following code (icache lines 366-371):
def read_insn_word(addr, data):
    print("addr ", addr)
    print("data ", data)
    word = addr[2:INSN_BITS+2]
    print("word ", word)
    return data[word * 32:32 + word * 32]

addr  (sig hit_nia)
data  (proxy (array [(sig $signal), (sig $signal), (sig $signal), (sig
$signal)]) (sig hit_way))
word  (slice (sig hit_nia) 2:3)

File "icache.py", line 1493, in elaborate
    replace_way, plru_victim, cache_out)
  File "icache.py", line 979, in icache_comb
    read_insn_word(r.hit_nia, cache_out[r.hit_way])
  File "icache.py", line 371, in read_insn_word
    return data[word * 32:32 + word * 32]
TypeError: slice indices must be integers or None or have an __index__ method


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