[Libre-soc-dev] Running the libre-soc CPU under cxxsim

Luke Kenneth Casson Leighton lkcl at lkcl.net
Tue Sep 8 09:09:50 BST 2020

crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Mon, Sep 7, 2020 at 11:34 PM Cesar Strauss <cestrauss at gmail.com> wrote:

> So, I think it would mean running the libre-SOC CPU under cxxsim.
> Can we do it? Which unit test gives the most coverage? Would it be
> src/soc/simple/test/test_issuer.py ?


i've added this:

+if True:
+    from nmigen.back.pysim import Simulator, Delay, Settle
+    from nmigen.sim.cxxsim import Simulator, Delay, Settle

so it is possible to flip easily without significant changes.

really this should be an environment variable

import os
      sim = Simulator(m, engine=os.environ.get('NMIGEN_SIM_MODE"))


More information about the Libre-soc-dev mailing list